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Edit File: opcodes.mo
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D %/ i j/ k Ô/ k @0 s ¬0 ( 1 ( I1 ( r1 * ›1 ( Æ1 ( ï1 * 2 ' C2 0 k2 0 œ2 + Í2 + ù2 + %3 * Q3 9 |3 + ¶3 â3 ý3 4 0 4 / J4 z4 ‰4 ˜4 ²4 Ì4 á4 ù4 5 5 &5 <5 N5 `5 , {5 ¨5 À5 Ü5 ó5 * 6 * :6 e6 " {6 ž6 ½6 É6 " è6 7 *7 E7 `7 ~7 E —7 E Ý7 6 #8 - Z8 4 ˆ8 3 ½8 ñ8 9 %9 79 I9 ^9 s9 ˆ9 9 ¹9 % É9 ï9 , : ' -: ' U: 1 }: 1 ¯: 9 á: 9 ; 1 U; 9 ‡; 9 Á; û; < # .< " R< " u< ˜< 0 µ< æ< 9 ü< 6= L= g= …= ž= ' ·= ß= ì= ÿ= # > 3> J> a> x> Ž> ž> ½> Ð> ã> ö> ? ? -? A? U? i? y? ‰? “? ¯? ¿? Ï? å? û? $ @ 3@ F@ b@ {@ ”@ ª@ À@ Î@ ! Ù@ û@ A $ !A # FA jA . |A / «A . ÛA B B -B IB YB uB ‘B ¬B ÌB åB 3 C 7 8C 4 pC ¥C ¯C ÅC ÌC ÛC êC D D 4D CD ] > ³ ‘ w z m x ± * L k ' ¥ n 6 Q d . r R ^ @ § ™ ¡ i s | h • t 8 5 V v ! … p K j 3 { C M P Ÿ : } % < 9 $ B “ ž A ( f – ? a _ ’ o ¯ N ` y ª \ ‡ D © ˆ e F - T Ž G « ~ ² l J 1 µ H — Y , Š £ ® ´ b ¦ 4 = ¤ + " & # ¢ ¬ ˜ I ” W c [ š ¨ S Œ ƒ † „ g ) U ‹ O X q ° ‚ E ; u 7 Z œ ‰ € / 2 0 › For the options above, The following values are supported for "ARCH": For the options above, the following values are supported for "ABI": aliases Do print instruction aliases. cp0-names=ARCH Print CP0 register names according to specified architecture. Default: based on binary being disassembled. debug_dump Temp switch for debug trace. fpr-names=ABI Print FPR names according to specified ABI. Default: numeric. no-aliases Don't print instruction aliases. reg-names=ABI Print GPR and FPR names according to specified ABI. reg-names=ARCH Print CP0 register and HWR names according to specified architecture. The following AARCH64 specific disassembler options are supported for use with the -M switch (multiple options should be separated by commas): The following ARM specific disassembler options are supported for use with the -M switch: The following MIPS specific disassembler options are supported for use with the -M switch (multiple options should be separated by commas): The following PPC specific disassembler options are supported for use with the -M switch: The following S/390 specific disassembler options are supported for use with the -M switch (multiple options should be separated by commas): The following i386/x86-64 specific disassembler options are supported for use with the -M switch (multiple options should be separated by commas): addr16 Assume 16bit address size addr32 Assume 32bit address size addr64 Assume 64bit address size att Display instruction in AT&T syntax data16 Assume 16bit data size data32 Assume 32bit data size dpfp Recognize FPX DP instructions. dsp Recognize DSP instructions. fpud Recognize double precision FPU instructions. fpus Recognize single precision FPU instructions. i386 Disassemble in 32bit mode i8086 Disassemble in 16bit mode intel Display instruction in Intel syntax spfp Recognize FPX SP instructions. suffix Always display instruction suffix in AT&T syntax x86-64 Disassemble in 64bit mode # <dis error: %08lx> $<undefined> %02x *unknown* %dsp16() takes a symbolic address, not a number %dsp8() takes a symbolic address, not a number %s: Error: %s: Warning: 'LSL' operator not allowed 'ROR' operator not allowed (DP) offset out of range. (SP) offset out of range. (unknown) *unknown* 21-bit offset out of range 64-bit address is disabled <function code %d> <illegal precision> <internal disassembler error> <internal error in opcode table: %s %s> <unknown register %d> ABORT: unknown operand Address 0x%s is out of bounds. Bad immediate expression Bad register in postincrement Bad register in preincrement Bad register name Don't know how to specify # dependency %s Error: read from memory failed Hmmmm 0x%x Immediate is out of range -128 to 127 Immediate is out of range -32768 to 32767 Immediate is out of range -512 to 511 Immediate is out of range -7 to 8 Immediate is out of range -8 to 7 Immediate is out of range 0 to 65535 Internal disassembler error Internal error: bad sparc-opcode.h: "%s", %#.8lx, %#.8lx Internal error: bad sparc-opcode.h: "%s", %#.8lx, %#.8lx Invalid position, should be 0, 16, 32, 48 or 64. Invalid position, should be 0, 8, 16, or 24 Invalid position, should be 0,4, 8,...124. Invalid position, should be 16, 32, 64 or 128. Label conflicts with `Rx' Label conflicts with register name Missing '#' prefix Missing '.' prefix Missing 'pag:' prefix Missing 'pof:' prefix Missing 'seg:' prefix Missing 'sof:' prefix Operand is not a symbol SR/SelID is out of range Syntax error: No trailing ')' Unknown error %d Unrecognised disassembler CPU option: %s Unrecognised disassembler option: %s Unrecognised register name set: %s Unrecognized field %d while building insn. Unrecognized field %d while decoding insn. Unrecognized field %d while getting int operand. Unrecognized field %d while getting vma operand. Unrecognized field %d while printing insn. Unrecognized field %d while setting int operand. Unrecognized field %d while setting vma operand. Value is not aligned enough Value must be a multiple of 16 Value must be in the range 0 to 240 Value must be in the range 0 to 28 Value must be in the range 0 to 31 Value must be in the range 1 to W keyword invalid in FR operand slot. W register expected Warning: disassembly unreliable - not enough bytes available address writeback expected bad instruction `%.50s' bad instruction `%.50s...' branch operand unaligned branch to odd offset branch value not in range and to odd offset branch value out of range displacement value is not aligned displacement value is out of range don't know how to specify %% dependency %s dsp:16 immediate is out of range dsp:20 immediate is out of range dsp:24 immediate is out of range dsp:8 immediate is out of range extraneous register floating-point immediate expected illegal bitmask illegal immediate value illegal use of parentheses imm10 is out of range imm:6 immediate is out of range immediate is out of range 0-7 immediate is out of range 1-2 immediate is out of range 1-8 immediate is out of range 2-9 immediate offset immediate out of range immediate value immediate value cannot be register immediate value is out of range immediate value out of range invalid conditional option invalid mask field invalid register invalid register for stack adjustment invalid register name invalid register offset invalid shift amount invalid shift operator jump hint unaligned junk at end of line missing `)' missing `]' missing mnemonic in syntax string missing register negative immediate value not allowed negative or unaligned offset expected offset(IP) is not a valid form operand is not zero operand out of range (%ld not between %ld and %ld) operand out of range (%ld not between %ld and %lu) operand out of range (%lu not between %lu and %lu) register element index register number register number must be even shift amount shift amount must be 0 or 12 shift amount must be 0 or 16 shift amount must be 0 or 8 shift amount must be a multiple of 16 shift operator expected stack pointer register expected syntax error (expected char `%c', found `%c') syntax error (expected char `%c', found end of instruction) unable to change directory to "%s", errno = %s undefined unexpected address writeback unknown unknown 0x%02lx unknown 0x%04lx unknown constraint `%c' unrecognized form of instruction unrecognized instruction vector5 is out of range vector8 is out of range Project-Id-Version: opcodes 2.28.90 Report-Msgid-Bugs-To: bug-binutils@gnu.org POT-Creation-Date: 2017-07-03 16:55+0200 PO-Revision-Date: 2017-11-25 20:10+0800 Last-Translator: Boyuan Yang <073plan@gmail.com> Language-Team: Chinese (simplified) <i18n-zh@googlegroups.com> Language: zh_CN MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Plural-Forms: nplurals=1; plural=0; X-Bugs: Report translation errors to the Language-Team address. X-Generator: Poedit 2.0.4 对于以上的选项，以下值å¯è¢«ç”¨äºŽ "ARCH"： 对于以上的选项，以下值å¯è¢«ç”¨äºŽ "ABI"： aliases è¦æ‰“å°æŒ‡ä»¤åˆ«å。 cp0-names=ARCH æ ¹æ®æŒ‡å®šçš„æž¶æž„æ‰“å° CP0 寄å˜å™¨å。 é»˜è®¤ï¼šæ ¹æ®è¢«å汇编的二进制代ç 。 debug_dump 调试跟踪的临时开关。 fpr-names=ABI æ ¹æ®æŒ‡å®šçš„ ABI 打å°æµ®ç‚¹å¯„å˜å™¨å。 默认：数å—。 no-aliases ä¸è¦æ‰“å°æŒ‡ä»¤åˆ«å。 reg-names=ABI æ ¹æ®æŒ‡å®šçš„ ABI 打å°é€šç”¨å¯„å˜å™¨å’Œæµ®ç‚¹å¯„å˜ å™¨å。 reg-names=ARCH æ ¹æ®æŒ‡å®šçš„æž¶æž„æ‰“å° CP0 å’Œ HWR 寄å˜å™¨å。 下列 AARCH64 特定的å汇编器选项å¯é€šè¿‡ -M 开关å¯ç”¨ï¼ˆä½¿ç”¨é€—å·åˆ†éš”多个选项）： 下列 ARM 特定的å汇编器选项å¯é€šè¿‡ -M 开关å¯ç”¨ï¼š 下列 MIPS 特定的å汇编器选项å¯é€šè¿‡ -M 开关å¯ç”¨ï¼ˆä½¿ç”¨é€—å·åˆ†éš”多个选项）： 下列 PPC 特定的å汇编器选项在使用 -M 开关时å¯ç”¨ï¼ˆä½¿ç”¨é€—å·åˆ†éš”多个选项）： 下列 S/390 特定的å汇编器选项å¯é€šè¿‡ -M 开关å¯ç”¨ï¼ˆä½¿ç”¨é€—å·åˆ†éš”多个选项）： 下列 i386/x86-64 特定的å汇编器选项在使用 -M 开关时å¯ç”¨ï¼ˆä½¿ç”¨é€—å·åˆ†éš”多个选项）： addr16 å‡å®š 16 ä½åœ°å€å¤§å° addr32 å‡å®š 32 ä½åœ°å€å¤§å° addr64 å‡å®š 64 ä½åœ°å€å¤§å° att 用 AT&T è¯æ³•æ˜¾ç¤ºæŒ‡ä»¤ data16 å‡å®š 16 ä½æ•°æ®å¤§å° data32 å‡å®š 32 ä½æ•°æ®å¤§å° dpfp 识别 FPX DP 指令。 dsp 识别 DSP 指令。 fpud 识别åŒç²¾åº¦ FPU 指令。 fpus 识别å•ç²¾åº¦ FPU 指令。 i386 在 32 ä½æ¨¡å¼ä¸‹å汇编 i8086 在 16 ä½æ¨¡å¼ä¸‹å汇编 intel 用 Intel è¯æ³•æ˜¾ç¤ºæŒ‡ä»¤ spfp 识别 FPX SP 指令。 suffix 在 AT&T è¯æ³•ä¸å§‹ç»ˆæ˜¾ç¤ºæŒ‡ä»¤åŽç¼€ x86-64 在 64 ä½æ¨¡å¼ä¸‹å汇编 # <å汇编出错: %08lx> $<未定义> %02x *未知* %dsp16() 使用一个符å·åœ°å€ï¼Œè€Œéžæ•°å— %dsp8() 使用一个符å·åœ°å€ï¼Œè€Œéžæ•°å— %s：错误： %s：è¦å‘Šï¼š ä¸å…许 'LSL' æ“作符 ä¸å…许 'ROR' æ“作符 (DP) å移é‡è¶Šç•Œ (SP) å移é‡è¶Šç•Œã€‚ (未知) *未知* 21ä½é•¿çš„å移é‡è¶Šç•Œ 64 ä½åœ°å€å·²ç¦ç”¨ <函数代ç %d> <éžæ³•çš„精度> <å汇编器内部错误> <æ“作数表ä¸å‡ºçŽ°å†…部错误：%s %s> <未知的寄å˜å™¨ %d> ä¸æ¢ï¼šæœªçŸ¥çš„æ“作数 åœ°å€ 0x%s 越界。 错误的立å³æ•°è¡¨è¾¾å¼ åŽç½®è‡ªå¢žä¸ä½¿ç”¨äº†é”™è¯¯çš„寄å˜å™¨ å‰ç½®è‡ªå¢žä¸ä½¿ç”¨äº†é”™è¯¯çš„寄å˜å™¨ 错误的寄å˜å™¨å ä¸çŸ¥é“如何指定 # ä¾èµ– %s 错误：从内å˜è¯»å–失败 å’¦... 0x%x ç«‹å³æ•°è¶Šç•Œ (-128 到 127) ç«‹å³æ•°è¶Šç•Œ (-32768 到 32767) ç«‹å³æ•°è¶Šç•Œ (-512 到 511) ç«‹å³æ•°è¶Šç•Œ (-7 到 8) ç«‹å³æ•°è¶Šç•Œ (-8 到 7) ç«‹å³æ•°è¶Šç•Œ (0 到 65535) å汇编器内部错误 内部错误：错误的 sparc-opcode.h：“%sâ€ï¼Œ%#.8lx，%#.8lx 内部错误：错误的 sparc-opcode.h：“%sâ€ï¼Œ%#.8lx，%#.8lx æ— æ•ˆçš„ä½ç½®ï¼Œåº”当为 0ã€16ã€32ã€48 或 64。 æ— æ•ˆçš„ä½ç½®ï¼Œåº”当为 0ã€8ã€16 或 24 æ— æ•ˆçš„ä½ç½®ï¼Œåº”当为 0ã€4ã€8ã€...ã€124。 æ— æ•ˆçš„ä½ç½®ï¼Œåº”当为 16ã€32ã€64 或 128。 æ ‡å·ä¸Žâ€˜Rxâ€™å†²çª æ ‡å·ä¸Žå¯„å˜å™¨åå†²çª ç¼ºå¤± '#' å‰ç¼€ 缺失 '.' å‰ç¼€ 缺失 'pag:' å‰ç¼€ 缺失 'pof:' å‰ç¼€ 缺失 'seg:' å‰ç¼€ 缺失 'sof:' å‰ç¼€ æ“作数ä¸æ˜¯ä¸€ä¸ªç¬¦å· SR/SelID 越界 è¯æ³•é”™è¯¯ï¼šæ²¡æœ‰ç»“尾的‘)’ 未知错误 %d æ— æ³•è¯†åˆ«çš„å汇编器 CPU 选项：%s æ— æ³•è¯†åˆ«çš„å汇编器选项：%s æ— æ³•è¯†åˆ«çš„å¯„å˜å™¨å称集：%s 建立 insn æ—¶é‡åˆ°æ— 法识别的å—段 %d。 解ç insn æ—¶é‡åˆ°æ— 法识别的å—段 %d。 获得 int æ“作数时é‡åˆ°æ— 法识别的å—段 %d。 获得 vma æ“作数时é‡åˆ°æ— 法识别的å—段 %d。 æ‰“å° insn æ—¶é‡åˆ°æ— 法识别的å—段 %d。 设置 int æ“作数时é‡åˆ°æ— 法识别的å—段 %d。 设置 vma æ“作数时é‡åˆ°æ— 法识别的å—段 %d。 数值对é½ç¨‹åº¦ä¸å¤Ÿ 值必须是 16 çš„å€æ•° 值必须在 0 到 240 çš„èŒƒå›´ä¸ å€¼å¿…é¡»åœ¨ 0 到 28 çš„èŒƒå›´ä¸ å€¼å¿…é¡»åœ¨ 0 到 31 çš„èŒƒå›´ä¸ å€¼çš„èŒƒå›´å¿…é¡»åœ¨ 1 到 W 关键å—éžæ³•ï¼Œåœ¨ FR æ“作数槽ä½ä¸ã€‚ 预期的 W 寄å˜å™¨ è¦å‘Šï¼šå汇编ä¸å¯é - 没有足够的å¯ç”¨å—节 预期的地å€å†™å›ž 错误的指令‘%.50s’ 错误的指令‘%.50s...’ 分支æ“ä½œæ•°æœªå¯¹é½ è·³è½¬å移é‡ä¸ºå¥‡æ•° 跳转越界且跳转å移é‡ä¸ºå¥‡æ•° 跳转越界 åç§»å€¼æœªå¯¹é½ å移值越界 ä¸çŸ¥é“如何指定 %% ä¾èµ– %s dsp:16 ç«‹å³æ•°è¶Šç•Œ dsp:20 ç«‹å³æ•°è¶Šç•Œ dsp:24 ç«‹å³æ•°è¶Šç•Œ dsp:8 ç«‹å³æ•°è¶Šç•Œ 多余寄å˜å™¨ 预期的浮点常é‡ç«‹å³æ•° éžæ³•çš„ä½æŽ©ç éžæ³•çš„ç«‹å³æ•° 括å·ç”¨æ³•éžæ³• imm10 越界 imm:6 ç«‹å³æ•°è¶Šç•Œ ç«‹å³æ•°è¶Šç•Œ 0-7 ç«‹å³æ•°è¶Šç•Œ 1-2 ç«‹å³æ•°è¶Šç•Œ 1-8 ç«‹å³æ•°è¶Šç•Œ 2-9 ç«‹å³æ•°å移 ç«‹å³æ•°è¶Šç•Œ ç«‹å³æ•° ç«‹å³æ•°ä¸èƒ½æ˜¯å¯„å˜å™¨ ç«‹å³æ•°è¶Šç•Œ ç«‹å³æ•°è¶Šç•Œ æ— æ•ˆçš„æ¡ä»¶é€‰é¡¹ æ— æ•ˆçš„æŽ©ç å—段 æ— æ•ˆçš„å¯„å˜å™¨ ç”¨äºŽè°ƒæ•´å †æ ˆçš„å¯„å˜å™¨æ— 效 æ— æ•ˆå¯„å˜å™¨å æ— æ•ˆçš„å¯„å˜å™¨åç§»é‡ æ— æ•ˆçš„ç§»ä½æ“作数 æ— æ•ˆçš„ç§»ä½æ“作符 跳转æç¤ºæœªå¯¹é½ è¡Œå°¾æœ‰åžƒåœ¾å—符 缺少‘)’ 缺少 `]' è¯æ³•å—符串ä¸æ²¡æœ‰åŠ©è®°ç¬¦ 缺失寄å˜å™¨ ä¸å…许负立å³æ•° 预期的负或未对é½çš„åç§»é‡ å移é‡ï¼ˆIP）ä¸æ˜¯åˆæ³•æ ¼å¼ æ“作数ä¸æ˜¯ 0 æ“作数越界(%ld ä¸åœ¨ %ld å’Œ %ld 之间) æ“作数越界 (%ld ä¸åœ¨ %ld å’Œ %lu 之间) æ“作数越界(%lu ä¸åœ¨ %lu å’Œ %lu 之间) 寄å˜å™¨å…ƒç´ ä¸‹æ ‡ 寄å˜å™¨æ•° 寄å˜å™¨æ•°å¿…须是å¶æ•° 移ä½æ“作数 移ä½é‡å¿…须为 0 或 12 移ä½é‡å¿…须为 0 或 16 移ä½é‡å¿…须为 0 或 8 移ä½é‡å¿…须是 16 çš„å€æ•° 预期的移ä½æ“作符 é¢„æœŸçš„å †æ ˆæŒ‡é’ˆå¯„å˜å™¨ è¯æ³•é”™è¯¯(需è¦å—符‘%c’，得到‘%c’) è¯æ³•é”™è¯¯(需è¦å—符‘%c’，å´åˆ°è¾¾æŒ‡ä»¤å°¾) æ— æ³•å°†å½“å‰ç›®å½•åˆ‡æ¢è‡³â€œ%sâ€ï¼Œerrno = %s 未定义 æ„外的地å€å†™å›ž 未知 未知 0x%02lx 未知 0x%04lx 未知的约æŸâ€˜%c’ æ— æ³•è¯†åˆ«çš„æŒ‡ä»¤æ ¼å¼ æ— æ³•è¯†åˆ«çš„æŒ‡ä»¤ vector5 越界 vector8 越界
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